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FuriosaAI
Physical Engineering (PI/PD) Engineer
Seoul, Seoul, South KoreaPosted 9 months agofulltime
What you'd do
- Evaluate PPA of chip designs as part of the architecture planning process collaboratively
- Perform synthesis,logic equivalence checking,SDC and UPF development,and static timing analysis
- Collaborate with design house teams to achieve optimal results in each chip tape-out
What they want
- Hold a BS in Electronic Engineering or related field with Verilog HDL design experience
- Bring 2 or more years of logic synthesis,LEC,STA,and SDC/UPF industry experience
- Use Synopsys tools including DC,FM,and PT with TCL and shell scripting skills
Nice to have
- Bring 5 or more years of ASIC design experience including DFT and Place and Route
- Apply knowledge of high-speed connectivity IPs such as PCIe,Ethernet,or HBM in designs
Seoulstart's read
- Visa tier (likely)
- E-7 specialty / professional (likely)
- Korean language
- Korean requirement not stated
- English friendliness
- High: JD in English, foreign-friendly signals
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