The short version
This is part 1 of a six-part series on the AI hardware industry. It assumes you know nothing about semiconductors, and it starts at the very bottom. By the end of the series you should be able to explain the whole supply chain to someone else: who makes what, why a handful of companies control the choke points, what physically limits how fast this can grow, and where Korea sits in all of it.
Nobody needs this knowledge to get through a day in Seoul. But if you live in Korea, this industry is quietly shaping your electricity bill, the national budget, the value of the won in your bank account, and the job market. It is worth understanding.
What a chip actually is
Start with sand. Ordinary sand is mostly silicon dioxide. Purify it far enough and you get silicon of a purity almost nothing else in manufacturing requires. Grow that into a single cylindrical crystal, slice the cylinder into discs about 30 centimetres across, and you have a wafer: the blank canvas every chip is built on.
Silicon is a semiconductor, which means it conducts electricity under some conditions and not others. That property lets you build a switch with no moving parts. Apply a small voltage to one terminal and current flows between two others. Remove it and the flow stops. That switch is a transistor, and it is the only thing a chip is really made of.
One transistor is a switch. Wire a handful together and you can build a circuit that performs simple logic: this AND that, this OR that, NOT this. Wire millions together and you can add numbers. Wire an enormous number together and you can run an AI model.
The scale here is hard to hold in your head. A high-end AI processor packs an immense number of transistors onto a piece of silicon roughly the size of a postage stamp, far more than a chip from even a few years ago. They are built not by placing them individually, which would be impossible, but by printing them: projecting a pattern of light onto a chemically coated wafer, developing it like photographic film, then etching and depositing material through the pattern. That printing step is called lithography, and it is the single hardest thing in the industry. Part 3 explains why one Dutch company has a complete monopoly on the EUV machines used for the most advanced layers.
Why "2nm" is not a measurement
You will constantly see chips described by a process node: 7nm, 5nm, 3nm, 2nm. It is natural to assume this is the size of something. It used to be. It has not been for well over a decade.
Today these are generation labels, closer to a car model year than a specification. A 2nm chip has no feature that is 2 nanometres wide. What the label communicates is that the manufacturer can pack transistors more densely than the previous generation, which typically buys better performance and lower power consumption for the same amount of work.
Two practical consequences follow. First, the names are not comparable between companies. One firm's 2nm is not automatically denser than another's 3nm, because each company names its own nodes. Second, the marketing name is a poor guide to whether a chip is any good. What matters is transistor density, power efficiency, and yield, meaning the percentage of chips on each wafer that come out working. Yield is the number manufacturers guard most closely, because a node with excellent specifications and poor yield loses money on every wafer.
Why AI needs a different kind of chip
Think about the difference between a small team of senior specialists and a stadium full of people with calculators.
A CPU is the small team. It has a modest number of powerful cores, each able to handle complicated, unpredictable instructions and make decisions about what to do next. That is exactly what running an operating system requires: lots of different tasks, each with its own logic, arriving in no fixed order.
A GPU is the stadium. It has a very large number of simple cores, each much less capable individually, all doing the same operation at the same moment on different pieces of data. GPUs were built for graphics, where the job is to work out the colour of two million pixels at once, and every pixel needs the same kind of calculation.
It turned out that AI has the same shape. Underneath the interface, running an AI model is overwhelmingly one operation: matrix multiplication, which is a structured way of multiplying big grids of numbers together and adding up the results. It is arithmetic a ten-year-old could do. There is just an unfathomable amount of it. That is a stadium problem, not a specialist-team problem, which is why the graphics-card industry accidentally found itself at the centre of artificial intelligence.
Not every AI chip is a GPU. Several large technology companies design their own accelerators that skip the graphics heritage entirely and target AI maths directly: Google's TPUs, Amazon's Trainium and Inferentia, Meta's MTIA. These are ASICs, application-specific integrated circuits, and the trade-off is the obvious one. They are more efficient at the narrow job they were built for and useless at anything else. Part 2 covers who builds these and why a company would take on the expense.
Training and inference are different problems
Almost every confusing claim about AI economics becomes clearer once you separate these two.
Training is building the model. You take an enormous quantity of text, images or other data, run it through a network holding an immense number of parameters, compare the output to the right answer, and nudge every parameter slightly in the direction that reduces the error. Then you do that again, and again, for an extended period across a very large number of chips running continuously. Training is a huge, concentrated, one-time cost. It is what people mean when they talk about a data center campus consuming as much electricity as a mid-sized city.
Inference is using the finished model. You send a question, the model reads its parameters, does its arithmetic, and produces an answer. Each individual inference is tiny compared to training. But it happens every single time anyone anywhere uses the product, which now means billions of times a day.
The industry spent 2023 and 2024 dominated by training demand. The centre of gravity has been shifting toward inference, because once a model exists, the cost of serving it never stops. This shift matters commercially: inference rewards efficiency and low cost per answer, which is a different competition from raw training performance, and it is the opening that specialised chip designers, including two Korean startups covered in part 6, are trying to exploit.
The memory wall, which is the whole story
Here is the thing that most explanations skip, and it is the reason Korea matters.
You would assume the limiting factor on an AI chip is how fast it can calculate. It usually is not. The processor can do arithmetic considerably faster than the rest of the system can supply it with numbers to work on. Feed it too slowly and the expensive processor sits idle, waiting. Engineers call this the memory wall.
The reason is physical. An AI model's parameters have to be stored somewhere, and there are far too many to keep inside the processor itself. So they live in memory chips nearby, and every calculation requires fetching them across a connection. That connection has a fixed width and a fixed speed. The amount of data it can carry per second is called bandwidth, and bandwidth is what runs out first.
An analogy that holds up: the processor is a chef who can cook astonishingly fast, and memory bandwidth is the width of the kitchen door. Hiring a faster chef does nothing if ingredients can only come through one at a time.
This is why memory stopped being a boring commodity. For decades, memory chips were sold largely on price per gigabyte, in a brutal cycle of gluts and shortages. AI changed the question from "how much can you store" to "how fast can you deliver it", and the companies that could answer the second question found themselves selling something much harder to replace.
What HBM is, concretely
The industry's answer to the memory wall is High Bandwidth Memory, or HBM. Three ideas, stacked literally and figuratively.
Go vertical. Instead of laying memory chips out side by side, stack them on top of each other, a dozen or more layers, into a tower.
Drill straight through. Connect the layers with thousands of vertical channels punched through the silicon itself, called through-silicon vias. This gives an enormously wider data path than routing signals around the edges.
Move it next door. Place the finished stack on the same package as the processor, a few millimetres away rather than a few centimetres, on a shared base layer that carries signals between them.
The result is a data path orders of magnitude wider than conventional memory offers. The cost is that this is genuinely hard to manufacture. You are bonding stacks of paper-thin silicon with microscopic alignment tolerances, and a single bad layer ruins the entire stack. Yields are lower and prices are far higher than for ordinary memory.
Only three companies make HBM at scale: SK Hynix, Samsung and Micron. Two are Korean. In the first quarter of 2026, Counterpoint Research put SK hynix at 58 percent of the HBM market, with Samsung and Micron at 21 percent each. That single statistic is most of the reason Korea is not a spectator in the AI boom.
From chip to data center
One more piece of vocabulary, because the scale jumps are where people get lost. Working outward:
The die is the piece of silicon itself, cut from the wafer.
The package is the die plus its HBM stacks, mounted together on a base that connects them, then sealed. When people say "chip" they usually mean this. Assembling it is called advanced packaging, and it is a bottleneck in its own right, covered in part 3.
The board and the server hold several packages together with CPUs, storage, power delivery and cooling, in a chassis that slides into a rack.
The rack is a cabinet of servers wired together so tightly that they behave as one large processor. This is where AI hardware stops resembling ordinary computing. A current-generation AI rack draws well over a hundred kilowatts, which is more than a small apartment building, concentrated into a cabinet about the size of a wardrobe. Air cannot remove that much heat, so these racks are cooled by liquid piped directly to the chips.
The cluster is thousands of racks connected by a specialised high-speed network, because training a large model means every chip constantly exchanging results with every other chip. The network is not plumbing here; it is part of the computer, and part 2 explains why that made networking chips a major business.
The data center is the building, the power feed, the cooling plant and the water supply. Increasingly the industry measures these in gigawatts of electrical capacity rather than square metres or server counts, which tells you what the real constraint has become. Part 4 is about that constraint.
Why the money got so large
To put a number on the demand: Nvidia reported record data center revenue of USD 75.2 billion for the single quarter ending in April 2026, up 92 percent from the same quarter a year earlier. That is one company, one product line, three months.
That figure exists because the four largest American cloud companies are collectively spending on a scale with few peacetime precedents, and because every one of those chips needs memory, packaging, networking, a building and a power connection. Each layer of that chain has its own leaders, its own economics and its own bottleneck.
Part 2 maps the whole chain, layer by layer, and names who leads each one.