The short version
Part 1 covered what an AI chip is and why memory bandwidth limits it. This part maps the supply chain. Nine layers, working from the most abstract to the most physical. For each one: what it does, who leads, and roughly by how much.
Keep one thing in mind as you read. The pattern that repeats at almost every layer is not "a competitive market with a leader." It is "one or two or three companies, and then a considerable gap." Part 3 explains why those positions are so durable.
Layer 1: Design software and intellectual property
Before a chip exists physically, it exists as a design containing tens of billions of transistors. No human draws that. It is generated, simulated and verified by software called EDA, for electronic design automation. Think of it as the computer-aided design tools of the chip world, except that they also simulate the physics and check that the result can actually be manufactured.
The market is small in revenue terms and enormous in leverage, because nothing gets designed without it. On TrendForce's 2021 numbers, the most recent breakdown published on a source we can stand behind, Synopsys held about 32 percent, Cadence about 30 and Siemens EDA about 13, roughly three-quarters of the market between them. The exact split has moved since; the structure has not. Synopsys and Cadence are near-equals, far ahead of everyone, with Siemens a clear third.
Alongside EDA sits chip intellectual property: pre-designed building blocks that designers license rather than create from scratch. Arm is the dominant name, supplying the CPU architecture used in most phones and, increasingly, in data center processors including Nvidia's own Grace CPU.
Who leads: Synopsys, Cadence, Siemens EDA. Arm in processor IP.
Where Korea sits: nowhere. Korea has no EDA company of consequence. Samsung and SK Hynix design their chips on American software. This is a real dependency and it appears again in part 5.
Layer 2: Chip design
This is the layer everyone has heard of. Companies here design accelerators and own no factories.
Nvidia is the centre of gravity, reporting USD 75.2 billion of data center revenue in the single quarter ending April 2026, up 92 percent year on year. Its advantage is not only the silicon. It is the combination of the chip, the networking that ties thousands together, the rack-scale system design, and CUDA, the software layer that AI researchers have been building on for the better part of two decades. Part 3 unpacks why that combination is so difficult to attack.
AMD is the main direct competitor, and it has real momentum. Its MI450 accelerator, built on TSMC's 2nm process, anchors a large agreement announced with OpenAI in October 2025, with the first tranche scheduled for the second half of 2026. In July 2026 AMD also announced a substantial investment in Anthropic as part of a compute arrangement.
The cloud companies design their own. Google has TPUs, now several generations deep and split across multiple manufacturing partners. Amazon has Trainium, whose third version became generally available in December 2025 and is the company's first 3nm chip. Meta has MTIA. The logic is straightforward: if you are going to spend a hundred billion dollars a year on compute, designing your own chip to avoid a supplier's margin starts to look reasonable, even at a cost of hundreds of millions per design.
The co-design specialists are the quiet giants here. Most cloud companies do not design their custom chips alone; they hire Broadcom or Marvell to do the hard engineering. Those two together hold roughly 95 percent of that market. Google's next TPU generation reportedly splits the work, with Broadcom on the training part and MediaTek on a lower-cost inference part, which is a fairly transparent attempt to avoid depending on a single partner.
Who leads: Nvidia by a distance, then AMD, with Broadcom and Marvell dominating custom designs.
Where Korea sits: thinly. Korea has no accelerator designer at global scale. Two startups, Rebellions and FuriosaAI, are the credible attempts, and part 6 assesses them honestly.
Layer 3: Manufacturing
Designs become silicon at a foundry. This layer is the most concentrated in the entire economy that is not a formal monopoly.
In the first quarter of 2026, TSMC held 72 percent of the foundry market, up from 70.4 percent the previous quarter, with a record USD 47.95 billion in combined revenue for the ten largest foundries that quarter. Samsung was second at 6.5 percent. By revenue, TSMC's foundry business is roughly eleven times the size of Samsung's.
At the leading edge, where AI chips are made, TSMC's position is stronger still, though no public breakdown measures the leading edge separately. It is expanding 2nm and A16 capacity at a rapid compound annual growth rate from 2026 through 2028, and it has committed a very large sum to its Arizona site, where volume production has been pulled forward.
Samsung's foundry ambitions rest heavily on its Taylor, Texas fab, anchored by a large, multi-year contract with Tesla signed in July 2025 covering the AI5 and AI6 chips. Tesla's AI6 is reportedly allocated entirely to Samsung's 2nm process there. Intel is attempting a return with its 18A process and has reported design wins, though its longer-term 14A node faces questions about demand.
Who leads: TSMC, overwhelmingly.
Where Korea sits: second, but a distant second. This gap is the central frustration of Korean industrial policy and part 6 treats it at length.
Layer 4: Memory
Covered in part 1, and the layer where Korea genuinely leads.
In ordinary DRAM, Counterpoint Research put Samsung at 39 percent in the second quarter of 2026, ahead of SK Hynix at 26 percent and Micron at 25 percent. That ranking moved sharply over the preceding year: SK Hynix had held 39 percent in the second quarter of 2025, and its share fell even as its revenue rose 214 percent, which tells you how fast the whole market was growing.
In HBM, the premium stacked memory that AI accelerators require, the first quarter of 2026 had SK hynix at 58 percent, with Samsung and Micron at 21 percent each.
Demand at this layer is extraordinary. Samsung and SK Hynix agreed with OpenAI to scale toward a very large volume of DRAM wafer starts per month for the Stargate programme, with supply arrangements running for several years.
Who leads: Samsung in DRAM, SK Hynix in HBM, Micron closing on both.
Where Korea sits: at the front. This is the layer that makes Korea structurally important rather than merely large.
Layer 5: Advanced packaging
Once you have a processor die and several HBM stacks, something has to join them into one component with connections dense enough not to recreate the memory wall. That is advanced packaging, and TSMC's version, called CoWoS, has been a hard limit on how many AI chips the world can produce.
The scale-up has been dramatic, with monthly capacity several times its late-2024 level by the end of 2026. Demand has grown just as fast, and even after all that expansion supply is expected to remain short of it. Reported capacity and demand figures for this layer circulate in mismatched units, monthly wafer capacity against annual package demand, so treat any single pairing of the two with caution.
This is the least visible layer to outsiders and one of the most consequential. For much of 2024 and 2025, the binding constraint on AI chip supply was not the processors and not the memory. It was the ability to bolt them together.
Who leads: TSMC, with ASE and Amkor significant in the broader packaging market.
Layer 6: Manufacturing equipment
Fabs do not build themselves. A single leading-edge fab is filled with machines from a handful of suppliers, and this layer contains the most extreme concentration anywhere in the chain.
ASML, based in the Netherlands, makes the extreme ultraviolet lithography machines required to print the finest features on advanced chips. There is no competing machine and no competing company. It also makes the large majority of all lithography systems, EUV and older generations alike. A standard Low-NA EUV system costs hundreds of millions of dollars; the newer High-NA generation costs substantially more. The company has raised its 2026 sales guidance twice over the course of the year.
Below ASML sit the other essential tool makers: Applied Materials and Lam Research (American), Tokyo Electron (Japanese) and KLA (American, in inspection). Together with ASML, those five supply the majority of all semiconductor manufacturing equipment.
Who leads: ASML absolutely in lithography, then Applied Materials, Lam, Tokyo Electron and KLA.
Where Korea sits: as a large customer and a small supplier. Korean firms provide only a modest share of the equipment used in Korean fabs.
Layer 7: Materials and chemicals
The least glamorous layer and a genuine strategic choke point. Chipmaking consumes ultra-pure wafers, photoresists (the light-sensitive coatings that make printing possible), specialty gases, polishing slurries and etchants, all to purity standards that very few companies can meet.
Japan dominates. Shin-Etsu and SUMCO together supply roughly 90 percent of the world's silicon wafers. Japanese firms including JSR, Tokyo Ohka Kogyo, Shin-Etsu and Fujifilm hold roughly 90 percent of the photoresist market.
Korea learned exactly how much this matters in 2019, when Japan restricted exports of three chemicals essential to Korean chipmaking. The response was a national localisation push, and it worked: hydrogen fluoride imports from Japan fell 66 percent by value within two years, and dependence on Japan for EUV photoresist fell below half. The global concentration in Japanese hands, though, is unchanged, and that is a separate problem from any one country's exposure.
Who leads: Japan, decisively.
Layer 8: Networking
Training a large model means thousands of chips constantly exchanging intermediate results. If the network between them is slow, the chips wait, and expensive silicon sits idle. At this scale the network stops being plumbing and becomes part of the computer.
Two approaches compete. Nvidia sells a tightly integrated stack: NVLink connecting GPUs within a rack at 1.8 terabytes per second per GPU on the fifth generation, and 3.6 on the sixth, plus InfiniBand or its Spectrum-X Ethernet between racks. Broadcom sells merchant Ethernet chips that anyone can build with, and supplies most of the high-end Ethernet switching silicon the industry buys. Its Tomahawk 6 switch runs at 102.4 terabits per second, with a roadmap to double and then double again.
The trend has been toward Ethernet for connections between racks, largely because cloud operators prefer not to depend on a single vendor. The next step is co-packaged optics, moving the optical components onto the switch package itself to cut power and cost.
Who leads: Nvidia inside the rack, Broadcom between them.
Layer 9: Data centers, clouds and electricity
Finally the physical buildings, and the power to run them.
The four largest US cloud companies plan an enormous combined capital expenditure in 2026, a sharp increase from 2025. Individual guidance ranges have moved upward repeatedly through the year at nearly every one of the four. Different trackers count different things and arrive at meaningfully different totals, so treat any single figure as an estimate. Part 4 covers the specific figures and how they have shifted.
Alongside them sits a newer category, the neoclouds, which exist to buy accelerators and rent them out. CoreWeave is the largest, reporting an enormous revenue backlog. Its last full-year filing put it at 43 data centers with 850 megawatts of active power and 3.1 gigawatts contracted, at the end of 2025.
And then there is the constraint that has quietly become the binding one. Note the unit in that last paragraph: gigawatts, not square metres. The industry now measures itself in electrical capacity because electricity is what runs out. Part 4 is entirely about this.
Who leads: Amazon, Microsoft, Google and Meta, with Oracle and the neoclouds as fast-growing challengers.
The pattern
Read the nine layers together and one thing stands out. This is not an industry of open competition with clear leaders. It is a chain of near-monopolies and tight oligopolies, arranged in series.
One company makes the machines that print advanced chips. One company manufactures most of them. Three companies make the memory. Three companies make the design software. Two Japanese companies make most of the wafers. Two companies design most custom accelerators.
Any one of those links can slow the entire chain, and none of them can be replaced quickly, because each rests on decades of accumulated engineering knowledge, extreme capital requirements, or both.
Part 3 examines the strongest of these positions and asks the obvious question: what exactly stops someone from competing?