Memory Layout Manager

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From Intel’s original posting

Job Details: Job Description: The Role and Impact We are seeking a skilled and motivated Layout Design Engineering Manager to lead a team of layout engineers in delivering best in class SRAM,RF,ROM,CAM Memory compiler designs across the Intel's bleeding FinFETs,GAA technologies. In this role, you will champion technical execution by overseeing compiler friendly and optimized floorplanning, high-density,performance based placement and routing template, and rigorous physical sign-off processes including DRC, LVS, Yield, DFM, Density, parasitic extraction, Noise Reliability i.e. EM, IR. You will provide technical guidance, set clear goals, and foster cross-functional collaboration with circuit design, Tilers, and foundry teams to meticulously optimize memory area, performance, power, and yield. Beyond daily execution, you will spearhead layout methodology innovations, establish advanced automation flows using SKILL, Python, or Tcl, and cultivate a culture of technical excellence by mentoring senior and staff-level engineers. The role requires a strong vision for leveraging AI and ML technologies (such as reinforcement learning for routing or predictive analytics for DRC debugging) to…