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DeepX
Design Verification Engineer
Seoul, South KoreaPosted 16 months ago
What you'd do
- Develop testbenches and perform simulations using SystemVerilog/UVM.
- Build verification environments and analyze functional coverage metrics.
- Analyze and fix digital circuit design issues through RTL review.
What they want
- Bachelor's degree or higher in Electrical Engineering or Computer Engineering.
- Minimum 3 years of experience in digital design and verification.
- Experience building verification environments using SystemVerilog and UVM.
Nice to have
- Experience in AI semiconductor or NPU design and verification.
- Proficiency in scripting languages (Python,Perl,TCL,or similar).
Seoulstart's read
- Visa tier (likely)
- E-7 specialty / professional (likely)
- Korean language
- Korean not required
- English friendliness
- High: JD in English, foreign-friendly signals
- Context