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DeepX
SoC Physical Design Engineer
Seoul, South KoreaPosted 11 months ago
What you'd do
- Perform RTL-to-GDSII physical design including synthesis,place and route,timing closure.
- Conduct low-power design and power optimization across chip architecture.
- Run physical verification (DRC,LVS,ERC) and signal integrity checks (SI,IR Drop,EM analysis).
What they want
- Bachelor's degree or higher in Electrical Engineering,Computer Engineering,or related field.
- 10+ years of ASIC physical design experience (or relevant project experience for new graduates).
- Proficiency with EDA tools such as Synopsys or Cadence (Design Compiler,ICC2,Innovus).
Nice to have
- Hands-on experience with 7nm or below advanced process technologies.
- Experience in high-performance or low-power chip design projects.
- Familiarity with scripting languages (Python,Perl,TCL) for design automation.
Seoulstart's read
- Visa tier (likely)
- E-7 specialty / professional (likely)
- Korean language
- Korean not required
- English friendliness
- High: JD in English, foreign-friendly signals