Job description preview
From Broadcom’s original posting
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom’s Core Switching Group division is seeking a candidate for a DFT engineer. Products include networking switches for Scale up and Scale Out for traditional and AI data centers. This position is at our R&D center in San Jose, CA. The successful candidate will have hands-on experience for DFT ATPG and mbist pattern debug and drive defect reduction, optimize wafer sort & final test, and maximize yield across our product portfolio. Responsibilities • DFT Pattern post-silicon support: ATPG and MBIST DFT patterns generation, bringup and debug • Yield Enhancement: Monitor wafer sort (CP) and final test (FT) yield, binning distribution, and parametric data. Drive continuous improvement plans to achieve aggressive yield and cost targets. • Root Cause Analysis: Perform scan diagnostic, mbist and repair debug, resolve yield excursions. Correlate electrical failures to inline fab metrology, defect density, and process tool data. • Failure…
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