6-8 years RTL design experience using SystemVerilog/Verilog (M.S. counts as 2 years,Ph.D. as 4 years).
Proven full design lifecycle experience: architecture through RTL,tape-out,silicon bring-up.
Hands-on high-speed link design at link or protocol layer (PCIe,CXL,Ethernet,proprietary D2D).
Nice to have
Direct experience with UCIe or other die-to-die interconnect standards.
Working understanding of SerDes-based high-speed links and digital PHY interfacing.
Design-for-Debug expertise: building testability,loopback modes,performance/error monitors.
Seoulstart's read
Visa tier (likely)
E-7 specialty / professional (likely)
Korean language
Korean not required
English friendliness
High: JD in English, foreign-friendly signals
Context
Rebellions is a deep-tech semiconductor chiplet startup with English-first operations; visa sponsorship and English-language work culture are standard,but senior technical alignment with Korean engineering leadership on standards-based D2D design is essential.
This is Seoulstart's analysis of the public job description, not the employer's stated policy. Verify visa sponsorship, language requirements, and remote allowances directly with the recruiter.