DeepX

SoC ASIC Design Engineer

Seoul, South KoreaRecently posted

Apply on DeepX's career page

What you'd do

Design SoC ASIC for AI hardware processors using Verilog and SystemVerilog RTL

What they want

RTL design expertise in Verilog or SystemVerilog
SoC design with ARM Core,AMBA bus,and interconnect architecture
Design and implementation of AMBA AXI bus interfaces

Nice to have

RTL synthesis,Static Timing Analysis,CDC checks,Lint,formal verification
System-level CDC-free Clock Generation Units and Reset Generation Units design
Extensive Engineering Change Order process experience

Seoulstart's read

Visa tier (likely): E-7 specialty / professional (likely)
Korean language: Korean requirement not stated
English friendliness: High: JD in English, foreign-friendly signals
Context: Series D pre-IPO AI semiconductor startup with strong global profile and CES recognition; technical role likely English-friendly despite Korean benefits section,but confirm visa sponsorship willingness upfront given specialized ASIC expertise demand.

This is Seoulstart's analysis of the public job description, not the employer's stated policy. Verify visa sponsorship, language requirements, and remote allowances directly with the recruiter.

View the full posting and apply on DeepX's career page

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