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DeepX
DDR Memory Subsystem SoC Engineer
Seoul, South KoreaPosted 11 months ago
What you'd do
- Integrate third-party DDR controller and PHY IPs into SoC RTL and verify wrapper logic.
- Verify protocol specifications and performance between SoC interconnect and memory controller.
- Define SoC-level timing constraints and collaborate with STA and physical design teams.
What they want
- Bachelor's degree or higher in Electrical or Computer Engineering or related field.
- Deep understanding of JEDEC DDR/LPDDR standards (DDR4/5,LPDDR4/5).
- Proficiency in scripting languages such as Python,Perl,and Tcl.
Nice to have
- Master's or Ph.D. degree.
- Multiple years of experience with DDR/LPDDR controller or PHY development.
- Hands-on experience with DDR subsystem bring-up and debugging on silicon.
Seoulstart's read
- Visa tier (likely)
- E-7 specialty / professional (likely)
- Korean language
- Korean not required
- English friendliness
- High: JD in English, foreign-friendly signals