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DeepX
SoC Design (MIPI, ISP & DSC Subsystem)
Seoul, South KoreaPosted 4 months ago
What you'd do
- Integrate ISP and MIPI CSI-2 interfaces for seamless front-end image processing pipeline.
- Collaborate with sensor vendors to optimize data reception and initial image signal processing.
- Integrate and verify Display Stream Compression IP blocks into MIPI subsystem.
What they want
- Proficiency in RTL implementation using Verilog or SystemVerilog for subsystem integration.
- Strong experience in IP-level and subsystem-level verification methodologies.
- Understanding of ISP pipeline stages (Demosaic,Noise Reduction,HDR,Color Correction).
Nice to have
- Experience applying NPU technologies to video processing tasks.
- Previous experience in system semiconductor or AI hardware industry.
- Experience filing patents or developing core IP portfolios.
Seoulstart's read
- Visa tier (likely)
- E-7 specialty / professional (likely)
- Korean language
- Korean requirement not stated
- English friendliness
- High: JD in English, foreign-friendly signals