Memory System Designer and Place and Route Engineer
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Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering. Job Responsibilities • Architect and design memory subsystems • Implement RTL of subsystem designs • Place and route (physical design) • Design closure: timing, DRC, LVS, EM/IR, etc. • Gate netlist synthesis Skill Set Required • Strong design skills • Ability to write and debug Verilog RTL code • Place and route expertise • Proficient in running STA, DRC, EM/IR tools, and attaining design closure • Ability to code in Python • Good understanding of synthesis tools and running synthesis • Capable of running and debugging logical equivalency checkers • Familiar with memory behavior • Proficient in writing automation scripts,…
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