What you'd do
- Define architecture and microarchitecture specs; own chip modules and RTL implementation.
- Converge design functionality and PPA across the chip.
- Implement RTL in SystemVerilog; optimize power,timing,and area.
What they want
- Hold Master's in EE,CS,or equivalent practical experience.
- Bring two plus years chip design with RTL,synthesis,verification,timing closure.
- Implement microprocessor simulators in depth using C++ or similar languages.
Nice to have
- Ph.D in EE,CS,or equivalent practical experience preferred.
- Prior accelerator design experience is a strong plus for applicants.
- Worked on highly pipelined and multiple clock domain designs.
Seoulstart's read
- Visa tier (likely)
- E-7 specialty / professional (likely)
- Korean language
- Korean not required
- English friendliness
- High: JD in English, foreign-friendly signals