ASIC VERIFICATION ENGINEER
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From Broadcom’s original posting
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job Description What You can Expect - - Work on Latest cutting edge CSG Switches. - To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem. - Develop and maintain verification Environment in Mix of SV/UVM. - Understanding of the End to End spec along with Network & System topology. - Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level. - Coverage Closures, Gate Level Simulations along with end to end verification cycle. What we are looking for - - Bachelor's/Masters/PhD with Verification experience of 8+ years - Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST - Exposure to any one of the scripting languages - Perl or Python or SED/Awk - Expertise in Co-Simulations (HW/SW) Flow and debugs - Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary. - Expertise in…
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