Job description preview
From Broadcom’s original posting
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs. Responsibilities include: • Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off • Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule • High proficiency in UVM Experience: • BSEE required, MSEE/PHD preferred • 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug. Compensation and Benefits The annual base salary range for this position is USD 101,000.00 To USD 162,000.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your…
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